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general description the max2741 l1-band gps receiver ic offers a high- performance, compact solution for mobile handsets, pdas, and automotive applications. total voltage gain of 80db and a 4.7db cascaded noise figure can pro- vide receiver sensitivity for applications requiring -185dbw for indoor tracking solutions. this dual-conversion receiver downconverts the 1575.42mhz gps signal to a 37.38mhz first if, and then a 3.78mhz second if. an integrated 2- or 3-bit adc (1- bit sign, 1- or 2-bit mag selectable) samples the sec- ond if and outputs the digitized signals to the baseband processor. the integrated synthesizer offers the flexibility in fre- quency planning to allow a single board design to be employed for reference frequencies from 2mhz to 26mhz. the integrated reference oscillator allows either tcxo or crystal operation. the receiver runs from a 2.7v to 3.0v supply, and draws only 30ma when active. it is offered in a 28-pin thin qfn package, and is specified for -40? to +85? at 3v. applications in-vehicle navigation systems (ivns) telematics (vehicle and asset tracking, inventory management) automotive security emergency response systems emergency road-side assistance location-based services/internet (pdas) digital cameras/camcorders recreational handhelds/walkie-talkies geographical information systems (gis) consumer electronics (location-based games) precision timing features ? supports all popular handset reference frequencies up to 26mhz ? 4.7db cascaded noise figure ? 80db cascaded gain ? tolerates -90dbm in-band jammer ? tolerates +13dbm cdma out-of-band jammer at device input ? integrated synthesizer and vco ? integrated 2- or 3-bit adc ? 50db if agc range ? small 28-pin thin qfn package ? spi control interface ? clock output for baseband processor max2741 integrated l1-band gps receiver ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 v cc 6 ifout+ ifout- ifin+ ifin- n.c. n.c. 8910 11 12 13 14 filt sclk cs sdi shdn xtal refclk 15 16 17 18 19 20 21 gpsclk gpsif2 gpsif1 gpsif0 v cc 5 n.c. sdo 7 6 5 4 3 2 1 gnd v cc 4 v cc 3 vco 3225.6mhz v cc 2 rfin n.c. v cc 1 lna 1612.8mhz 33.6mhz 16.8mhz 200khz 90 0 /96 /192 /2 /16128 p.d. /r ref osc adc spi interface max2741 mux pin configuration/ functional diagram ordering information 19-3559; rev 0; 1/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. spi is a trademark of motorola, inc. part temp range pin-package MAX2741ETI -40? to +85? 28 thin qfn 5 . 0 m m x 5 . 0 m m 2 8 - p i n t h i n q f n evaluation kit available
max2741 integrated l1-band gps receiver 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (operating conditions (unless otherwise specified): v cc = 2.7v to 3.0v; refclk driven with 10mhz sinusoid, 1.2v p-p ; registers set according to mode; no rf input signal; digital baseband outputs left open; t a = -40? to +85?. typical values are measured at v cc = 2.75v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc pins to gnd ...................................................-0.3v to +3.3v v cc pins to each other .........................................-0.3v to +0.3v filt to gnd................................................-0.3v to (v cc + 0.3v) cmos inputs to gnd (shdn, sclk, cs , sdi).................................................+0.3v to (v cc + 0.3v) cmos outputs to gnd (clkout, gpsif_, sdo).........................................-0.3v to (v cc + 0.3v) rfin to gnd...............................................-0.3v to (v cc + 0.3v) first if filter i/o to gnd (ifout? ifin? .....-0.3v to (v cc + 0.3v) crystal inputs to gnd (xtal, refclk).....-0.3v to (v cc + 0.3v) maximum rf input power...................................................0dbm continuous power dissipation (t a = +85?) 28-pin thin qfn (derate 20.8mw/? above +70?) .1000mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +160? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units supply voltage 2.7 3.0 v normal operation (t a = +25?) 30 42 supply current standby (v shdn = v il , synth:d8 = 0) 0.7 ma input-logic high threshold v cc - 0.1 v input-logic low threshold 0.1 v input-logic high/low current -10 +10 ? output-logic high i load = 100? v cc - 0.3 v output-logic low i load = 100? 0.3 v ac electrical characteristics (operating conditions (unless otherwise specified): v cc = 2.7v to 3.0v for t a = -40? to +85?; refclk driven at 10mhz sinusoid, 1.2v p-p ; registers set according to mode; using the typical application circuit ; cw rf signal at 1575.42mhz. typical values are mea- sured at v cc = 2.75v, t a = +25?.) parameter conditions min typ max units 1st conversion stage (rf to 1st if) rf frequency l1-band 1575.42 mhz rf conversion gain (note 1) 15 21 32 db noise figure mid-gain (config1:d4?0 = 10000) 4.7 db input ip3 (note 2) -30 dbm rf image rejection (notes 3, 4) 20 35 db lo leakage at rf lo to rfin pin -90 dbm caution! esd sensitive device
max2741 integrated l1-band gps receiver _______________________________________________________________________________________ 3 ac electrical characteristics (continued) (operating conditions (unless otherwise specified): v cc = 2.7v to 3.0v for t a = -40? to +85?; refclk driven at 10mhz sinusoid, 1.2v p-p ; registers set according to mode; using the typical application circuit ; cw rf signal at 1575.42mhz. typical values are mea- sured at v cc = 2.75v, t a = +25?.) parameter conditions min typ max units 2nd conversion stage (1st if to adc input) 1st if frequency at ifout 37.38 mhz max gain (config1:d4?0 = 11111) (note 1) 48 61 74 db conversion gain min gain (config1:d4?0 = 00000) (note 1) 10 db input ip3 1st conversion (note 5) -36 dbm noise figure max gain (config1:d4?0 = 11111) 12 db real 0.40 ms if output port admittance imaginary 1.5 pf real 0.40 ms if input port admittance imaginary 0.15 pf (synth:d13?10 = 1111) 2.9 lpf -3db corner frequency (synth:d13?10 = 0000) 7.7 mhz synthesizer i cp_oh pll charge-pump source current 75 ? i cp_ol pll charge-pump sink current -100 ? closed-loop phase noise at 1khz offset -55 dbc/hz comparison spurs at ?00khz offset -44 dbc/hz reference oscillator frequency sinusoid (note 1) 2 10 26 mhz ref input voltage level sinusoid (note 1) 0.6 2.2 v p-p vco coarse tune range programmable (config1:d7 to d5 = 000 to 111) (note 1) 240 mhz digital i/o spi clock frequency 1 mhz note 1: production tested for +25? and +85?, guaranteed by design and characterization for -40?. note 2: test tones at 1575.8mhz and 1576.8mhz at -60dbm/tone. note 3: guaranteed by design and characterization. note 4: image frequency is 1575.42mhz + 2(f if ) = 1650.18mhz note 5: test tones at 37.38mhz and 36.88mhz at -50dbm/tone.
max2741 integrated l1-band gps receiver 4 _______________________________________________________________________________________ pin description pin name function 1v cc 1 lna supply connection. external rf bypass capacitor to ground required. 2, 20, 22, 23 n.c. reserved. make no connections to this pin. 3 rfin lna input. connect to gps antenna through a bandpass filter. this input requires an external matching network to match to 50 ? . ac-couple to this pin. 4v cc 2 vco supply connection. external rf bypass capacitor to ground required. 5v cc 3 cml supply connection. external rf bypass capacitor to ground required. 6v cc 4 digital logic and pll supply connection. external rf bypass capacitor to digital ground required. 7 gnd ground. connect to pc board digital ground plane. 8 filt pll loop filter connection. this is the output of the phase detector? charge pump. use the recommended filter on ev kit for optimal phase noise and lock time. 9 sclk spi clock input (cmos) 10 cs spi chip-select input (cmos, active low) 11 sdi spi data input (cmos) 12 shdn full ic power-down. this shutdown pin disables the on-chip oscillator and the rest of the ic. to keep the oscillator running, use the software shutdown (synth:d8); (cmos, active high). 13 xtal crystal oscillator feedback capacitor connection 14 refclk reference clock input for pll. drive with 1.2v p-p when using tcxo module. 15 gpsclk gps clock output to baseband. this is the clock used by the adc to sample the gps data (cmos). 16 gpsif2 sampled if output, bit 2 (cmos). see table 5. 17 gpsif1 sampled if output, bit 1 (cmos). see table 5. 18 gpsif0 sampled if output, bit 0 (cmos). see table 5. 19 v cc 5i f supply connection. external rf bypass capacitor to ground required. 21 sdo spi data output (cmos) 24 ifin- 1st if input (inverting). connect this 2.5k ? differentially terminated input to the 1st if filter? (-) output. 25 ifin+ 1st if input (noninverting). connect this 2.5k ? differentially terminated input to the 1st if filter? (+) output. 26 ifout- 1st if output (inverting). connect this 2.4k ? differential output to the 1st if filter? (-) input. 27 ifout+ 1st if output (noninverting). connect this 2.4k ? differential output to the 1st if filter? (+) input. 28 v cc 6 rf image-reject mixer supply. external rf bypass capacitor to ground required. exposed gnd rf ground. ultra-low inductance connection to ground. place several vias to pc board ground plane.
max2741 integrated l1-band gps receiver _______________________________________________________________________________________ 5 detailed description the max2741 gps offers a high-performance super- heterodyne receiver solution for low-power mobile devices, with the benefit of using the system? existing clock reference. this receiver is ideal for integration into mobile phone handsets using common reference fre- quencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and 26.0mhz. the only external components required are the gps rf filter, an if filter (typically designed from inexpen- sive discretes), a three-component pll loop filter, and a few other resistors and capacitors. the max2741 inte- grates the reference oscillator core, the vco and its tank, the synthesizer, a 1- to 3-bit adc, and all signal path blocks except for the 1st if filter. the typical application area for the receiver is less than 2cm 2 . rf/1st conversion stage (front-end) the max2741 rf front-end lna and mixer are the most important in the signal path. this stage sets the noise figure for the receiver, defining the sensitivity, and mixes the 1575.42mhz l1-band gps signal down to a 1st if of 37.38mhz. the lna itself has an nf of approximately 1.5db; the cascaded nf of the front-end (including the mixer) is approximately 4.7db, and the cascaded gain is typically 21db. the image-reject mixer is set up for a high-side injected rflo (1612.80mhz), and offers typically better than 30db rejection of the image noise (1650.18mhz). the -30dbm input 3rd-order intercept (iip3) of the rf strip, in conjunc- tion with the gps if filter, provides excellent out-of-band interferer immunity. the 1st if outputs (ifout? are internally biased to approximately 2v, and have a differential source impedance of approximately 2.5k ? . the if filter can be implemented as a discrete l/c filter, or as a monolithic saw or ceramic if one is available. if/2nd conversion stage the 2nd conversion stage consists of an active mixer, a variable-gain amplifier (vga), and a tunable lowpass filter. the if mixer is configured for low-side lo injec- tion for a 2nd if of 3.78mhz. total gain in this stage is 62db, and the vga offers 51db of gain adjustment. the vga is typically controlled by the baseband ic through the spi interface to optimize the signal swing for digiti- zation by the adc. the on-chip lowpass filter has an adjustable cutoff fre- quency, programmable from 2.9mhz to 7.7mhz in 16 steps. this lpf further reduces out-of-band noise and band-limits the signal to the adc, ensuring that the sampling process does not generate alias components. dc offset compensation at the adc input is performed by an on-chip 4-bit dac. this compensates for any dc error introduced by transistor mismatch in the differential stage driving the adc input, allowing the downconverted gps signal? dc level to be centered within the threshold volt- ages of the adc. adc the on-chip adc samples the down-converted gps signal at the 2nd if (3.78mhz). sampled output is pro- vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit (2-bit magnitude, 1-bit sign) formats, as determined by the adc mode configuration bit (config1:d15); see table 5 for details. the adc sample clock (system gps clock) is derived either directly from the reference clock (synth:d9 = 1), or from an rflo divide-by-96 block to provide a 16.8mhz sample clock (synth:d9 = 0). the clock is available to the baseband processor at gpsclk (pin 15). the sampled adc data bits are available on pins 16, 17, and 18 (gpsif2, gpsif1, and gpsif0). the functionality of the pins is different in each mode (2-bit vs. 3-bit)?ee table 5 in determining the interface connection for the application circuit. synthesizer the max2741 integrates an integer-n synthesizer; all blocks except the loop filter are on-chip. the reference can be either a crystal (driven by the internal oscillator), or a tcxo module. the oscillator provides a 5pf load to the crystal. a tcxo module should provide a swing in the 0.6v p-p to 2.2v p-p range. the reference divider (/r) is programmable (synth: d7?0), and can accommodate reference frequencies up to 26mhz. the reference divider needs to be set so the comparison frequency (f comp ) at the frequency/ phase detector is 200khz. the vco runs at twice the fre- quency of the rflo; the rflo is therefore generated from the vco using a quadrature divide-by-2 block. the rf lo is f comp x 8064 (typically 1612.80mhz), and the 1st if lo is f comp x 168 (typically 33.6mhz); the rf and if lo division ratios are not adjustable. this configuration allows for the use of reference frequencies common to gsm, cdma, tdma, td-scdma, and umts handsets: 9.6mhz (r = 48), 13.0mhz (r = 65), 14.4mhz (r = 72), 19.2mhz (r = 96), 26.0mhz (r = 130), etc.
max2741 integrated l1-band gps receiver 6 _______________________________________________________________________________________ the vco offers a bank of tuning capacitors that can be latched in/out to adjust the center frequency. because the system does not require any rf lo frequency change (i.e., changing channels), the vco varactor tun- ing gain is very low by design, which means the tuning range of the vco is narrow. the coarse-tune capacitors in the tank circuit allow the system to adjust the vco center frequency as needed to guarantee that the syn- thesizer can lock. in practice, process and temperature effects on vco centering are negligible, and a coarse- tune setting of 110 (config:d7 to d5) will center the vco tuning range correctly in virtually all cases. to aid in bench and prototype testing, the pfd offers out-of-lock- high and out-of-lock-low indicators, available in the spi status register (status:d9 to d8). use these flags to determine if the vco tuning range needs to be adjusted higher or lower in the case where the pll cannot lock. the pll filter is the only external block of the synthesizer. the typical filter is a classic c-r-c two-pole shunt network on the tune line. low phase noise is preferred at the expense of longer pll settling times, so a low 10khz to 20khz loop bandwidth is used. the recommended pll 10khz filter implementation, with charge pump set to 200? (config1:d10 = 1), is shown in figure 1. the system/gps clock is derived either directly from the reference oscillator, or synthesized from the rflo (see the adc section). this clock is used as the sam- pling clock for the on-chip adc, and is seen at pin 15, gpsclk. spi bus, address and bit assignments an spi-compatible serial interface is used to program the max2741 for configuring the different operating modes. in addition, data can be read out of the max2741 for sta- tus and diagnostic use. the serial interface is controlled by four signals: sclk (serial clock), cs (chip-select), sdi (data input), and sdo (data output). the control of the pll, agc, test, offset management, and block selection is performed through the spi bus from the baseband controller. a 20-bit word, with the msb (d15) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. the spi bus has four control lines: serial clock (sclk), chip-select ( cs ), data in (sdi), and data out (sdo). enable sdo functionality by setting the digital test bus bits: config1:d9 to d8 = 01. the timing of the inter- face signals is shown in figure 2 and table 1 along with typical values for setup and hold time require- ments. for best performance, the spi bus should be configured during the startup initialization and then left with the opti- mum values in the registers. any changes to the adc and vga bits during gps signal processing may cause glitches and corrupt the analog signal path. reading from the spi bus does not interrupt gps operation. 6 v cc 4 7 gnd 89 filt sclk max2741 22nf 36k ? 100pf figure 1. recommended 3rd-order pll filter lsb msb cs sclk sdi t setupd t hdata t period t end t setupss figure 2. spi timing diagram table 1. spi timing requirements symbol parameter typ value units t setupd data to sclk setup 20 ns t period sclk period 100 ns t hdata data hold to sclk 20 ns t setupss cs to sclk disable 20 ns t end falling sclk to cs inactive 20 ns
max2741 integrated l1-band gps receiver _______________________________________________________________________________________ 7 table 2. register address and data bit assigments (write) data address register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 synth reserved lpf autotune initiate lpf tuning word (msb) lpf tuning word lpf tuning word lpf tuning word (lsb) xtal clock select standby pll ref div ratio (msb) pll ref div ratio pll ref div ratio pll ref div ratio pll ref div ratio pll ref div ratio pll ref div ratio pll ref div ratio (lsb) 010 0 config 1 adc mode adc offset control (lsb) adc offset control adc offset control (msb) adc offset control (sign) double charge- pump current digital test bus mode select (msb) digital test bus mode select (lsb) vco coarse tuning range (msb) vco coarse tuning range vco coarse tuning range (lsb) agc gain (msb) agc gain agc gain agc gain agc gain (lsb) 010 1 config 2 reset cmos drive vco low drive vco high reserved reserved reserved reserved reserved reserved reserved reserved analog test mode select analog test mode select analog test mode select analog test mode select analog test mode select 011 0 table 3. register address and data bit assigments (read) data address register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 status reserved reserved reserved reserved reserved reserved out-of-lock (high) out-of-lock (low) xtal clock selected parity reserved lpf auto- calibrate end lpf autotune (msb) lpf autotune lpf autotune lpf autotune (lsb) 011 1
max2741 integrated l1-band gps receiver 8 _______________________________________________________________________________________ detailed register definitions table 4. detailed register definition for write address 0100: synth data bit default description d15 1 reserved d14 1 lpf autotune initiate: i = initiate autotune, 0 = manual tuning. d13?10 0100 lpf tuning word: 0000 ~ 7.7mhz, 1111 ~ 2.9mhz. d9 1 xtal clock select: 1 = external reference, 0 = synthesized 16.8mhz. d8 0 standby: 0 = normal operating mode, 1 = standby (oscillator remains active), but only if d9 = 1. d7?0 01100000 reference division ratio. default 19.2mhz external reference (r = 96dec). r = f ref / 200khz. table 5. detailed register definition for write address 0101: config 1 data bit default description d15 1 adc mode. select 1 for 1-bit magnitude and sign, select 0 for 2-bit magnitude and sign. 1: gpsif2 = sign, gpsif1 = magnitude, gpsif0 = x 0: gpsif2 = msb magnitude, gpsif1 = lsb magnitude, gpsif0 = sign d14?11 0000 adc offset control (approx 4mv/step): d14 = lsb, d12 = msb, d11 = sign. d10 0 double charge-pump current: 0 = 100?, 1 = 200?. d9 to d8 00 digital test bus mode select. see table 9 for test-mode descriptions. d7 to d5 001 vco coarse tuning range. 000 = lowest frequency, 111 = highest frequency. d4?0 11111 agc gain. digital control of the agc amplifier in the 2nd if section. 00000 => min gain, 11111 => max gain (linear gain ~2.5db per unit spi word). table 6. detailed register definition for write address 0110: config 2 data bit default description d15 1 reset cmos: 0 = hold cmos dividers in reset and pfd is tri-stated, 1 = inactive. d14 1 drive vco low: 0 = active, forces vco to lowest frequency. n.b. do not activate both d14 and d13 at the same time. d13 1 drive vco high: 0 = active, forces vco to highest frequency. n.b. do not activate both d14 and d13 at the same time. d12?7 100000 reserved d6 to d5 11 must be programmed to 11 d4?0 11111 analog test mode select: reserved
max2741 integrated l1-band gps receiver _______________________________________________________________________________________ 9 applications information fundamentally, the only application areas that require careful consideration are the lna input match and the 1st if filter. of course, proper supply bypassing, grounding, and layout is required for reliable perfor- mance from any rf circuit. lna input matching input matching is critical for optimum noise figure and system sensitivity. optimum source impedance (as seen from the lna input) for lowest noise figure is 29 ? + j47 ? . remember that optimum noise match and optimum gain match (return loss) do not occur simultaneously, so a good application circuit will sacrifice gain slightly in favor of reduced noise figure. gain and noise circles are pro- vided in figure 3; s11 tabular data is provided in table 8. 1st if interface and filtering the typical application uses a 37.38mhz 1st if, and employs an if filter. the order of the filter should be tai- lored to suit the applicationstand-alone gps receivers will not require the channel-selection and stopband attenuation of gps receivers that are inte- grated into other wireless handsets. be sure that the fil- ter topology provides dc-blocking for the if i/o ports. table 7. detailed register definition for read address 0111: status data bit default description d15?10 xxxxxx reserved d9 x out-of-lock (high frequency): 1 = pll is out of lock, vco free-running at its highest frequency, 0 = locked. d8 x out-of-lock (low frequency): 1 = pll is out of lock, vco free-running at its lowest frequency, 0 = locked high. d7 1 xtal clock selected: 1 = synthesized 16.8mhz reference, 0 = external clock. d6 x parity: 1 = even, 0 = odd. d5 x reserved d4 x lpf autotune end: 0 = autotune run ended; 1 = calibrating or manual tuning. d3?0 xxxx lpf autotune: 0000 ~ 7.7mhz; 1111 = 2.9mhz. table 8. max2741 s11 g = gmax - 1db nf = nfmin + 0.2db figure 3. gain and noise circles for max2741 lna input freq (mhz) s11 (mag) s11 (? 1100 0.874 -50.9 1200 0.867 -56.1 1300 0.859 -61.5 1400 0.842 -66.9 1500 0.821 -72.3 1550 0.809 -74.9 1560 0.806 -75.4 1570 0.804 -75.9 1575 0.803 -76.2 1580 0.801 -76.4 1590 0.799 -77.0 1600 0.796 -77.5 1650 0.783 -80.0 1700 0.768 -82.5 1800 0.739 -87.4 1900 0.708 -92.3 2000 0.677 -96.8
max2741 integrated l1-band gps receiver 10 ______________________________________________________________________________________ 28 27 26 25 24 23 22 v cc 6 ifout+ ifout- ifin+ ifin- n.c. n.c. 8910 11 12 13 14 filt sclk cs sdi shdn xtal refclk 15 16 17 18 19 20 21 gpsclk gpsif2 gpsif1 gpsif0 v cc 5 n.c. sdo 7 6 5 4 3 2 1 gnd v cc 4 v cc 3 v cc 2 rfin n.c. v cc 1 max2741 sdo sd1 cs sclk gpsif0 gpsif1 gpsif2 gpsclk refclk baseband ic rf i/o connection receiver rf bpf rfin lna input rf bpf output if i/o connection receiver if filter ifout+ 1st if output from mixer (+) if bpf input, 2.5k ? differential ifout- 1st if output from mixer (-) if bpf input, 2.5k ? differential ifin+ 1st if input (+) if bpf input, 2.5k ? differential ifin- 1st if input (-) if bpf input, 2.5k ? differential baseband i/o connection receiver bb ic/mac sclk cmos input cmos output cs cmos input cmos output sdi cmos input cmos output sdo cmos output cmos input shdn cmos input cmos output gpsclk cmos output cmos input gpsif0 cmos output cmos input gpsif1 cmos output cmos input gpsif2 cmos output cmos input synthesizer i/o connection receiver external components filt pll phase-detector charge-pump pll loop filter xtal crystal oscillator feedback feedback capacitors refclk external tcxo or crystal analog (also connected to refclk input to mac) t ypical interface diagram interface summary all i/o connections are dc-coupled. supply voltages as specified in the electrical specifications.
max2741 integrated l1-band gps receiver ______________________________________________________________________________________ 11 digital test bus the digital test bus (dtb) is provided to allow for easy bench analysis of the digital workings of the receiver. t ypical application circuit v cc 6 ifout+ ifout- ifin+ ifin- n.c. n.c. filt sclk cs sdi shdn xtal refclk gpsclk gpsif2 gpsif1 gpsif0 v cc 5 n.c. sdo gnd v cc 4 v cc 3 v cc 2 rfin n.c. v cc 1 v cc gps rf input from gps bpf v cc v cc v cc 2.2pf 100pf 22pf 100pf 22pf v cc 1nf 100pf 220pf 100nf 100pf 1nf 100pf 6.2nh spi data out to baseband processor gps data and clock to baseband processor 22nf 36k ? 100pf h/w shutdown line from baseband processor spi clock and data into baseband processor system tcxo (2mhz to 26mhz) v cc 100pf 22pf 39pf 470 h 470 h 39pf 680pf 5.6pf 680pf 680pf 5.6pf 680pf 100pf 28 27 26 25 24 23 22 8910 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 vco 3225.6mhz lna 1612.8mhz 33.6mhz 16.8mhz 200khz 90 0 /96 /192 /2 /16128 p.d. /r ref osc adc spi interface max2741 mux table 9. digital test-mode-select description digital output function mode register setting config1:d9 to d8 gpsif2 gpsif1 gpsif0 31 1 sign lsb msb 21 0m counter r counter handshake status 10 1 charge pump up charge pump down sdo 00 0c ml clock calibrate lpf end xtl clock selected
max2741 integrated l1-band gps receiver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e xxxxx marking g 1 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- l common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 y 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 n 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 y 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. g 2 2 21-0140 package outline, 16, 20, 28, 32l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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